The present invention relates generally to the fields of semiconductor devices and processing. Particularly, it concerns semiconductor devices, and processes for forming the same, that involve field isolation regions. Even more particularly, it concerns semiconductor devices, and processes for forming the same, that involve two or more field isolation regions having different characteristics on the same chip.
Integrated circuit fabrication usually requires that individual active and passive circuit elements be electrically isolated from one another. The isolation allows for circuit connections to be made with patterned surface metallization, the isolated circuit elements being in contact with that metallization. Many diverse techniques have been proposed to achieve effective field isolation, ranging from junction isolation, dielectric isolation, and combinations thereof. Although each technique has its advantages, shortcomings nevertheless remain.
As more functional elements are placed on a single chip, it becomes difficult to manufacture isolation regions that satisfy the needs of each functional element. This is especially true when each function element requires isolation constraints. In particular, for a system-on-a-chip solution, both logic and memory devices may be present on a single chip. In this case, it may be particularly difficult to manufacture satisfactory isolation regions for each device type. Specifically, though both logic and memory devices require a large device densities, the isolation requirements for the two devices may be quite different.
For instance, memory devices often require trenches with rounded trench corners while logic devices often require narrow isolation, with the rounded nature of the corners being less important. Memory devices typically require rounded trench corners to avoid electrical field enhancement at the trench corners during program and erase steps. The enhanced fields are sought to be avoided because they may lead to several problems including, but not limited to the reduction of bit cell endurance and reliability. In contrast to the requirements of memory devices, logic devices typically do not require trench-corner rounding, or not to the degree necessary in memory devices. Thus, as may be seen in this one example, the field isolation requirements for a single chip may be quite varied. This variation, in turn, creates manufacturing difficulties especially since tradition isolation techniques process all different isolation regions similarly, if not identically. Thus, using traditional techniques, it is difficult or impossible to custom tailor different field isolation regions upon a single chip.
One existing technique to produce rounded trench corners involves growing a thick trench liner oxide at high temperature. A thick trench oxide liner produces trench corners with varying degrees of curvature; however, it is common for a thicker liner to also grow into the trench spacing itself. This growth within the trench may unfortunately reduce the gap distance between the trench walls, which increases the aspect ratio of the trenches that need to be filled by a trench fill oxide process. As the aspect ratio increases, it becomes more difficult to fill the trench, and the likelihood of imperfections in the trench increases.
As long as the spacing between the active regions is as large as it is in memory devices typically available today, trench liner thicknesses do not usually degrade the trench fill process. However, with increasing circuit densities in logic circuits likely to be seen in near-future devices, it will become increasingly more difficult to fill narrow trenches that have thick trench liners. In particular, attempts to fill such narrow trenches may lead to increased occurrence of voids (spaces within the trench that are not adequately filled by an insulator), which are problematic for many reasons. For instance, voids can cause electrical shorts during subsequent processing steps. Further, voids can collect polishing residue during polishing steps, which can lead to an entirely different set of problems. Voids can also collect excessive moisture, which leads to other problems. Finally, voids may collect one or more conducting materials from subsequent processing steps, which may also cause shorts.
Although generally recognizing certain problems associated with filling trenchesxe2x80x94the difficulty in filling narrow trenches and the inability to process isolation regions differently on a single chipxe2x80x94existing technology nevertheless utilizes single trench integration methods. Single trench integration methods, although such methods may exhibit at least a degree of utility in solving certain problems in the art, the specific problems mentioned above generally remain. Therefore, it would be advantageous to provide for the ability to create different isolation regions trenches having different characteristics (such as depth, corner rounding, etc.) on a single chip. This ability would provide for the effective de-coupling of, for instance, the isolation regions for logic and memory devices on a single chip. Having such an ability, both logic and memory devices may be adequately filled without the formation of voids using a standard oxide process or any CVD oxide fill process.
Problems enumerated above are not intended to be exhaustive, but rather are among many that tend to impair the effectiveness of previously known devices and techniques concerning isolation regions. Other noteworthy problems may also exist; however, those presented above should be sufficient to demonstrate that methodology appearing in the art have not been altogether satisfactory. In particular, existing techniques do not adequately account for the need for different types of devices to require different types of isolation. Because existing techniques process isolation regions together, it is difficult, if not impossible to form isolation regions with different characteristics on a single chip. That being the case, one or more isolation regions are often inadequately formed; for instance, one or more trench regions may be difficult or impossible to fill without the formation of voids. The voids, in turn, may have adverse affects on device performance.